The timing between the testbench and the design must be carefully synchronized.
At the cycle level, signals need to be driven and sampled at the correct time relative to the clock.

• Driving too late or sampling too early causes the testbench to miss a cycle.

• Within the same time slot (e.g., at time 100 ns), mixing design and testbench events may lead to race conditions — such as reading and writing the same signal simultaneously.

  • Question: do you read the old value or the new one?

In Verilog, nonblocking assignments (<=) helped mitigate this when the testbench drove the DUT.
However, it was still not guaranteed that the testbench sampled the latest driven value from the design.

SystemVerilog introduces constructs that improve timing control for communication between the testbench and design.